1. Field of the Invention
The present invention relates to a positioning/wiring method for a flip-chip semiconductor device and, more particularly, to a positioning/wiring method for a flip-chip semiconductor device in which a layout design method for input and output buffers (to be referred as input/output buffers hereinafter) is improved.
2. Description of the Prior Art
FIG. 1 is a plan view showing the arrangement of an ASIC chip such as a gate array or a cell base IC based on a positioning/wiring method of this type. Referring to FIG. 1, according to a popular positioning/wiring method, pads (chip terminals) 45 are arranged on the outermost peripheral portion of a chip 41h, input/output buffers 42d are arranged inside the pads 45, and desired functional circuits (to be referred to as internal circuits hereinafter) are arranged in a remaining inner region 62. A software algorithm for a CAD tool for performing automatic positioning/wiring processing has been studied on the basis of this positioning/wiring method.
In this method, the input/output buffers 42d are not arranged together with internal circuits arranged in the internal circuit region 62 in an automatic positioning process, and only the manner of arranging the input/output buffers 42d at specific one-dimensional positions in the peripheral region of the chip 41h must be considered. Therefore, a positioning technique different from that for positioning of blocks on a two-dimensional surface in an internal circuit block layout position definition step (step 75) for the internal circuit region 62 is used for positioning the input/output buffers 42d.
A conventional design procedure will be described with reference to the flow chart of FIG. 2. After an operation check on function description data on the function level is completed in function level simulation (step 71), logic synthesis is performed (step 72), and the resultant data is converted into circuit diagram data having circuit blocks as constituent elements (step 73). The size of an LSI chip is calculated from the circuit diagram data (step 74). In addition, as shown in FIG. 1, the layout positions of the input/output buffers 42d and layout positions 63 of internal circuit blocks are defined independently on the basis of the calculated size (step 75).
The input/output buffers and the internal circuit blocks are arranged (step 77) in a floor plan formation process (step 76) in accordance with the layout position definitions.
An internal circuit block 43a (consisting of 12 cells) in FIG. 1 is one of the internal circuits arranged in this manner. The wiring lengths between the internal circuit blocks are temporarily determined on the basis of this floor plan, and inappropriate paths are extracted by timing simulation (step 79). The floor plan is corrected to eliminate the inappropriate paths on the basis of the extraction result, and automatic positioning/wiring of all the circuits is executed on the basis of the floor plan (step 80). Actual wiring length timing simulation (step 81) is performed between the automatically positioned/wired circuits. If there is an inappropriate path, the layout is finely adjusted again to output mask data.
Consider the relationship between the size of an internal circuit of an ASIC and the number of chip terminals. With the advances in process techniques, the circuit size per unit area has increased almost double for each technology generation with a reduction in design rule and formation of multilevel interconnections. In contrast to this, the number of chip terminals based on wire bonding increases as the bonding tools improve and the pitch of bonding pads decreases. However, this increase in the number of chip terminals does not match the increase in the density of internal circuits. As a result, the number of chip terminals per circuit size decreases steadily for each technology generation.
Consider the possibility of improvement in the above point in conventional techniques associated with methods of arranging input/output buffers and chip terminals as well as ASICs. Japanese Unexamined Patent Publication No. 3-97238 discloses an example of the possibility. This gazette shows the idea of arranging chip terminals outside and inside an input/output buffer layout region on the periphery of a chip (see FIG. 1 in the gazette). In this case, a film carrier having inner leads is considered as a connection means in place of wire bonding.
Another example is disclosed in Japanese Unexamined Patent Publication No. 2-244755. This gazette discloses a case wherein two rows of input/output buffers are arranged on the periphery of a chip in a stacked state (see FIGS. 1 and 2 in the gazette). In this case, chip terminals are connected by a bonding technique. As shown in FIG. 2 in the gazette, in particular, the structure in which pads are also arranged in two rows is realized as a stereoscopic structure by changing the height of each bonding wire.
Still another example is disclosed in Japanese Unexamined Patent Publication No. 4-196464. This gazette discloses a case wherein arrays of input/output pads are arranged at predetermined intervals on transistors in a chip and on a wiring region surface (see FIG. 1 in the gazette). However, the gazette discloses no specific positions of input/output buffers and no specific method of connecting the input/output pads as chip terminals to an external unit.
Still another example is disclosed in Japanese Unexamined Patent Publication No. 4-357849. This gazette discloses a case wherein solder balls are formed as chip terminals on the entire surface of a chip in the form of arrays to perform flip-chip bonding (see FIGS. 1 and 2 in the gazette). The gazette discloses nothing about the positions of element on the chip.
Each of the above conventional techniques has the following drawbacks from the viewpoint of ASICs. First of all, in the conventional ASIC positioning/wiring method, since input/output buffers are arranged on the peripheral portion of a chip, the number of input/output buffers and the size of an internal circuit are uniquely determined as relative amounts by the size of each cell and a chip size.
If, for example, the size of an internal circuit is large, the length of the peripheral portion becomes long, and many input/output buffers can be arranged. If, however, the number of input/output buffers required for the LSI is small as compared with the size of the internal circuit, a space is produced in the peripheral portion. In contrast to this, if the size of the internal circuit is small, and the number of input/output buffers is relatively large, a space is produced in the internal circuit region, although the length of the peripheral portion increases for input/output buffers. In either case, the chip size includes a space, and hence the chip cost becomes high as compared with a case wherein no space is included.
In order to reduce the formation of such a space, an internal circuit may be arranged to partly protrude into a space on the peripheral portion, and rows of input/output buffers may be stacked in a space in the internal circuit region. In the ASIC technique, however, an automatic positioning/wiring tool must be effectively applied to such a structure.
Consider the above space reducing methods from such a viewpoint. In the former case, interconnections cannot be effectively arranged on a convex portion of the internal circuit region which protrudes into the peripheral portion of the chip. This is because the existing algorithms for tools are based on the premise that an overall internal region is rectangular.
In the latter case, since the density of chip terminals arranged near input/output buffers increases, it is difficult to perform packaging by a wire boding method which is generally used at present and hence is low in cost. For this reason, an algorithm for stacked rows of input/output buffers is not used for general ASIC products, and there is no general automatic position/wiring tool based on this structure.
That is, the layout structures of various chips, which have been proposed as an effective means for increasing the density of chip terminals, cannot be applied to ASICs, one of the features of which is automatic design, unless a new automatic process tool based on these structures is developed. In designing an ASIC chip with a higher area efficiency, the above limitations are posed in the conventional techniques.